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SG2525A SG3525A
REGULATING PULSE WIDTH MODULATORS
.8TO35VOPERATI .5. .100HzTO500KHzOSCI .SEPARATEOSCI .ADJUSTABLEDEADTI .I .PULSE.I .LATCHI .DUALSOURCE/
ON 1 V REFERENCE TRIMMED TO 1 % LLATOR RANGE LLATOR SYNC TERMINAL ME CONTROL NTERNAL SOFT-START BY-PULSE SHUTDOWN NPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS NG PWM TO PREVENT MULTIPLE PULSES SINK OUTPUT DRIVERS
DIP16
16(Narrow)
DESCRIPTION The SG3525Aseries of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor betweenthe CT andthe dischargeterminals provide a wide range of dead time ad- justment. Thesedevicesalso featurebuilt-insoft-startcircuitry with only an external timing capacitor required. A shutdownterminal controls both the soft-start circuity and the output stages, providing instantaneous
turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltagelockoutwhich keepsthe outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includesapproximately 500 mV of hysteresisfor jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525Aoutputstage features NOR logic, giving a LOW output for an OFF state.
PIN CONNECTIONS AND ORDERING NUMBERS (top view)
Type SG2525A SG3525A
Plastic DIP SG2525AN SG3525AN
SO16 SG2525AP SG3525AP
June 2000
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SG2525A-SG3525A
ABSOLUTE MAXIMUM RATINGS
Symbol Vi VC IOSC Io IR IT Supply Voltage Collector Supply Voltage Oscillator Charging Current Output Current, Source or Sink Reference Output Current Current through CT Terminal Logic Inputs Analog Inputs Total Power Dissipation at Tamb = 70 C Junction Temperature Range Storage Temperature Range Operating Ambient Temperature : SG2525A SG3525A Parameter Value 40 40 5 500 50 5 - 0.3 to + 5.5 - 0.3 to Vi 1000 - 55 to 150 - 65 to 150 - 25 to 85 0 to 70 Unit V V mA mA mA mA V V mW C C C C
P tot Tj Tstg Top
THERMAL DATA
Symbol Rth j-pins Rth j-amb R th j-alumina Parameter Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina (*) Max Max Max SO16 DIP16 50 80 50 Unit C/W C/W C/W
* Thermalresistance junction-alumina with the device soldered on themiddle ofan alumina supporting substrate measuring 15 x 20 mm ; 0.65mm thickness with infinite heatsink.
BLOCK DIAGRAM
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ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified)
Symbol Parameter Test Conditions Min. REFERENCE SECTION VREF V REF V REF Output Voltage Line Regulation Load Regulation Tj = 25 C Vi = 8 to 35 V IL = 0 to 20 mA Over Operating Range Line, Load and Temperature VREF = 0 Tj = 25 C 10 Hz f 10 kHz, Tj = 25 C Tj = 125 C, 1000 hrs Tj = 25 C Vi = 8 to 35 V Over Operating Range RT = 200 K CT = 0.1 F RT = 2 K CT = 470 pF IRT = 2 mA Tj = 25 C Sync Voltage = 3.5 V 400 1.7 3 0.3 1.2 2 3.5 0.5 2 1 0.5 1 RL 10 M Gv = 0 dB T j = 25 C 60 1 1.1 75 2 1.5 0.2 3.8 VCM = 1.5 to 5.2 V Vi = 8 to 35 V 60 50 5.6 75 60 0.5 3.8 60 50 1 2.8 2.5 5 10 1 60 1 1.1 75 2 1.5 0.2 5.6 75 60 0.5 2.2 5 80 40 20 2 0.3 3 5.05 5.1 10 20 20 5.15 20 50 50 5.2 100 200 50 6 1 6 120 400 1.7 3 0.3 1.2 2 3.5 0.5 2 1 2 1 1 2.8 2.5 10 10 1 2.2 4.95 80 40 20 2 1 3 5 5.1 10 20 20 5.2 20 50 50 5.25 100 200 50 6 2 6 120 V mV mV mV V mA Vrms mV % % % Hz KHz mA V s V mA mV A A dB MHz ms V V dB dB SG2525A Typ. Max. Min. SG3525A Typ. Max. Unit
VREF/T* Temp. Stability * Total Output Variation Short Circuit Current * VREF* *, * *, * f/T* fMIN fMAX *, * *, * Output Noise Voltage Long Term Stability Initial Accuracy Voltage Stability Temperature Stability Minimum Frequency Maximum Frequency Current Mirror Clock Amplitude Clock Width Sync Threshold Sync Input Current VOS Ib Ios * *, Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain Gain Bandwidth Product DC Transconduct. Output Low Level Output High Level CMR PSR Comm. Mode Reject. Supply Voltage Rejection
OSCILLATOR SECTION * *
ERROR AMPLIFIER SECTION (VCM = 5.1 V)
30 K RL 1 M Tj = 25 C
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ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Conditions Min. PWM COMPARATOR Minimum Duty-cycle * * * Maximum Duty-cycle Input Threshold Input Bias Current Soft Start Current Soft Start Low Level Shutdown Threshold VSD = 0 V, VSS = 0 V VSD = 2.5 V To outputs, VSS = 5.1 V Tj = 25 C VSD = 2.5 V Tj = 25 C Isink = 20 mA Isink = 100 mA Output High Level Under-Voltage Lockout IC tr* t f* Is Collector Leakage Rise Time Fall Time Supply Current Isource = 20 mA Isource = 100 mA Vcomp and Vss = High VC = 35 V C L = 1 nF, Tj = 25 C C L = 1 nF, Tj = 25 C Vi = 35 V 100 50 14 18 17 6 0.6 25 Zero Duty-cycle Maximum Duty-cycle SHUTDOWN SECTION 50 0.4 0.8 0.4 0.2 0.2 1 19 18 7 8 200 600 300 20 100 50 14 80 0.7 1 1 0.5 0.4 2 18 17 6 0.6 25 50 0.4 0.8 0.4 0.2 0.2 1 19 18 7 8 200 600 300 20 80 0.7 1 1 0.5 0.4 2 A V V mA s V V V V V A ns ns mA 45 0.7 49 0.9 3.3 0.05 3.6 1 0 45 0.7 49 0.9 3.3 0.05 3.6 1 0 % % V V A SG2525A Typ. Max. Min. SG3525A Typ. Max. Unit
Shutdown Input Current VSD = 2.5 V * Shutdown Delay Output Low Level OUTPUT DRIVERS (each output) (VC = 20 V)
TOTAL STANDBY CURRENT
* These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production.
*
Tested at fosc = 40 KHz (RT = 3.6 K, CT = 10nF, RD = 0 ). Approximate oscillator frequency is defined by : f= 1 CT (0.7 RT + 3 RD)
.DCt
ransconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : G v = gM RL whereRL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded.
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TEST CIRCUIT
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RECOMMENDED OPERATING CONDITIONS (*)
Parameter Input Voltage (Vi) Collector Supply Voltage (VC) Sink/Source Load Current (steady state) Sink/Source Load Current (peak) Reference Load Current Oscillator Frequency Range Oscillator Timing Resistor Oscillator Timing Capacitor Dead Time Resistor Range
*
Value 8 to 35 V 4.5 to 35 V 0 to 100 mA 0 to 400 mA 0 to 20 mA 100 Hz to 400 KHz 2 K to 150 K 0.001 F to 0.1 F 0 to 500
( ) Range over which the device is functional and parameter limits are guaranteed.
Figure 1 : Oscillator Charge Time vs. RT and C T .
Figure 2 : Oscillator Discharge Time vs. RD and C T .
Figure 3 : Output Saturation Characteristics.
Figure 4 : Error Amplifier Voltage Gain and Phase vs. Frequency.
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Figure 5 : Error Amplifier.
PRINCIPLES OF OPERATION SHUTDOWN OPTIONS (see Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 A to turn off the outputs.This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternateapproachis the useof the shutdowncircuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immediately set providing the fastest turn-off signal to the outputs ; and a 150 A current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation.
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Figure 6 : Oscillator Schematic.
Figure 7 : Output Circuit (1/2 circuit shown).
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Figure 8. Figure 9.
For single-ended supplies, the driver outputs are grounded.The VC terminal is switched to groundby the totem-pole source transistors on alternate oscillator cycles. Figure 10.
In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. Figure 11.
Thelow source impedanceof the outputdrivers provides rapid charging of Power Mos input capacitance while minimizing external components.
Low power transformers can be driven directly. Automaticresetoccurs duringdeadtime, whenboth ends of the primary winding are switched to ground.
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SG2525A-SG3525A
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.51 0.77
mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 0.030
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050
DIP16
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DIM. MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 0.35 0.19 0.1
mm TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.5 45 (typ.) 10 6.2 1.27 8.89 4 5.3 1.27 0.62 8(max.) 0.150 0.181 0.016 0.386 0.228 0.014 0.007 0.004 MIN.
inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010 0.020
OUTLINE AND MECHANICAL DATA
0.394 0.244 0.050 0.350 0.157 0.209 0.050 0.024
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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